The invention relates to a processor circuit comprising a first processor and provided with a parallel address input and a parallel data in/output, both for linkage to a second processor, and with a serial in/output for linkage to a digital network, which first processor is provided with
a first serial processor in/output which, via a converter circuit, is linked to the serial in/output of the processor circuit, and PA1 a second serial processor in/output which, via a receiving/transmitting circuit for converting parallel information into serial information and vice versa, is linked to the parallel address input and to the parallel data in/output. PA1 a first parallel address input which is linked to a parallel address output of the first processor, PA1 a first parallel data in/output which is linked to a parallel data in/output of the first processor, PA1 a second parallel address input which is linked to the parallel address input of the processor circuit, PA1 a second parallel data in/output which is linked to the parallel data in/output of the processor circuit. PA1 receiving an auxiliary program from the second processor, PA1 storing the auxiliary program in a first section of the dual memory means, which first section is situated, beginning at a start address, in address space belonging to the first processor, PA1 receiving a main program via a second section of the dual memory means, PA1 storing the main program in a memory linked to the first processor, which memory is situated, beginning at a further address, in address space belonging to the first processor, and then PA1 replacing the further address by the start address. PA1 a first serial processor in/output which, via a converter circuit, is linked to the serial in/output of the processor circuit, and PA1 a second serial processor in/output which, via a receiving/transmitting circuit for converting parallel information into serial information and vice versa, is linked to the parallel address input and to the parallel data in/output. PA1 a first parallel address input which is linked to a parallel address output of the first processor, PA1 a first parallel data in/output which is linked to a parallel data in/output of the first processor, PA1 a second parallel address input which is linked to the parallel address input of the processor circuit, PA1 a second parallel data in/output which is linked to the parallel data in/output of the processor circuit. PA1 receiving an auxiliary program from the second processor, PA1 storing the auxiliary program in a first section of the dual memory means, which first section is situated, beginning at a start address, in address space belonging to the first processor, PA1 receiving a main program via a second section of the dual memory means, PA1 storing the main program in a memory linked to the first processor, which memory is situated, beginning at a further address, in address space belonging to the first processor, and then PA1 replacing the further address by the start address.
A processor circuit of this type is generally known. It can be, for example, a personal computer card or PC card via which a PC processor (the second processor) is linked to an ISDN network (the digital network). On the PC card (the processor circuit) there is situated, for example, a 68302 processor (the first processor), a first serial processor in/output of which is linked via ISDN chips (the converter circuit) to a serial in/output of the PC card for connection to the ISDN network, and a second serial processor in/output of which is linked, via a UART (Universal Asynchronous Receiver Transmitter, the receiving/transmitting circuit for converting parallel information into serial information and vice versa), to a parallel address in/output and to a parallel data in/output of the PC card. These two in/ outputs can be linked to the PC processor. Such a PC card is eminently suitable for modem applications, as it is very simple for the 68302 processor to interpret the commands, such as, for example, Hayes commands, which are to be received from the PC processor via the UART.
This known processor circuit has the drawback that it is relatively difficult in a processor circuit of this type to perform error diagnoses, which should take place frequently, particularly during test phases.